在 Perl 中处理时间，很多模块，很方便，但是刚开始玩的人，可能没有发现合适的模块，所以使用起来感觉很麻烦。这里给大家推荐一下一个模块 strftime。
我们在推荐前，介绍一下 Perl 下取时间的今生前世吧。以前我想大家都是使用的 localtime 来取得当地日期时间和日期。这个函数如果在标量环境时，会以字符串的形式来传回目前的时间和日期 。默认的 localtime 的函数是以 1970...
DownloadOfficial website of Environment Modules
Download software source code: modules-5.4.0.tar.gz
Installation1234tar xvf modules-5.4.0.tar.gzconfiguremakesudo make install
The default installation ...
Design Level
Strategies
Operating System Level
Portioning, Power down
Software Level
Regularity, locality, concurrency
Architecture Level
Pipelining, Redundancy, data encoding
Circuit/...
本文旨在记录一次STA timing closure过程中如何利用Excel表格工具可视化的优化inter-clock skew，从而大大降低DMSA timing ECO的代价。
【Background】
这次timing closure的难点在于design有5个同步异频的clock。所谓同步异频是指这5个clock的source clock相同，但是经过了不同的clock divider...
Dynamic Power
Switching Power: This is the power spent charging and discharging the capacitance of the output net; it is also called load power or CV2 power. Since switching power is a function of ...
123456set_data_check -0.05 \ -fr [get_pins $related_pin] \ -to [get_pins $constrained_pin]set_multicycle_path -hold -1 \ -to [get_pins $constrained_pin]
Above script constrains the skew between $re...
set_multicycle_path path_multiplier [-setup|-hold] [-start|-end] -from -through -to Default path_multiplier: Setup 1, Hold 0.Setup: Regarding to EndClock by Default. (-end is the default)Hold: Regar...
When HDL Compiler reads in a Verilog or VHDL RTL description of the design, it translatesthe design into a technology-independent representation (GTECH). In GTECH, bothregisters and latches are repres...