本文旨在记录一次STA timing closure过程中如何利用Excel表格工具可视化的优化inter-clock skew，从而大大降低DMSA timing ECO的代价。

【Background】

这次timing closure的难点在于design有5个同步异频的clock。所谓同步异频是指这5个clock的source clock相同，但是经过了不同的clock divider, clock gating, 以及clock mux。clock structure简化为如下图所示：

• Generated clock从PLL出来就分叉：OCV严重
• PLL clock频率巨高：>1000MHz
• 三个clock group两两之间都有talk：CLK0, CLK1_0/CLK1_1/CLK1_2, CLK2。

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Dynamic Power

• Switching Power: This is the power spent charging and discharging the capacitance of the output net; it is also called load power or CV2 power. Since switching power is a function of switching activity and load capacitance, it is data dependent.
• Internal Power (Short Circuit Power/Crowbar Power): This is the power dissipated inside the gate when switching. This power is also called short power or crowbar power.

Static Power

• Static power is the power consumed by a device when no signals are changing values. Since static power consumption is primarily caused by leakage, in CMOS devices, Static Power is also known as Leakage Power. This is the power dissipated whenever the device is powered, regardless of activity; there are several sources of leakage power but they are all lumped together into a single value for modeling purposes. The amount of leakge power dissipated by a gate can depend on the logic state of the inputs. This is called “state-dependent leakage power“; most tools can model this if it is described in the library data.

Power Components

• Combinational: Combinational cell and a net driven by the combinational cell
• Sequential: Registers, Latch, ICG and the output net of the sequential logic
• Clock: Clock network
• IO: IO pad cell and the output net of the IO cell
• Memory: Memory and the output nets of the memory cell
• Macrocell:
• Blackbox:

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set_data_check -0.05 \
  -fr [get_pins $related_pin] \
  -to [get_pins $constrained_pin]

set_multicycle_path -hold -1 \
  -to [get_pins $constrained_pin]

Above script constrains the skew between $related_pin and $constrained_pin no more than 0.1ns, where $related_pin is like a clock pin whereas $constrained_pin is like a data pin.

As neither -setup nor -hold specified, it implies that both setup and hold checks are set as -0.05ns.

set_multicycle_path path_multiplier [-setup|-hold] [-start|-end] -from -through -to
Default path_multiplier: Setup 1, Hold 0.
Setup: Regarding to EndClock by Default. (-end is the default)
Hold: Regarding to StartClock by Default. (-start is the default)
In single clock domain design there is no meaning to the -start and -end flags. !!!
Note: In case your setup path_multiplier is X, use the path_multiplier of X-1 for
hold. In any case check out the report of your multicycles and the report exceptions
(Plus the report_exceptions -ignore) results.

Table 1 describes how the check points for setup and hold timing are moved back-
ward of forward depend on the -start/-end flags and the path_multiplier.

PrimeTime Multicycle Path Quick UG

When HDL Compiler reads in a Verilog or VHDL RTL description of the design, it translates
the design into a technology-independent representation (GTECH). In GTECH, both
registers and latches are represented by a SEQGEN cell, which is a
technology-independent model of a sequential element as shown in the figure below. SEQGEN
cells have all the possible control and data pins that can be present on a sequential element.

Knowing this is important and useful when you would set constraint on a register in the synthesis phase of HDL mapping, e.g.,

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set_multicycle_path -from [get_pins A_Example_reg/clocked_on]
set_false_path -to [get_pins B_Example_reg/next_state]

Refer to the document of ‘Design Compiler Optimization Reference Manual’ for details.

There are some useful options of command report_timing, which I haven’t been aware of before.

-start_end_pair

This option should be quite useful if you want to report violations from all startpoints to endpoints. By default report_timing only report the most critical startpoint to a certain endpoint even if -nworst is specified. With the option of -start_end_pair all startpoints will be shown up.

-path_type summary

Reports timing summary only with startpoints and endpoints.

-start_end_type reg_to_reg | reg_to_out | in_to_reg | in_to_out

Restricts the report to one of four classes.

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#
# Create a shell script which starts the license server
#
% cat /path/to/eda/script/snpslmd.sh
admin=eda
su $admin -c "/path/to/lmgrd -l $logfile -c $licfile"

#
# Create systemd service file
#
% cat /etc/systemd/system/snpslmd.service
[Unit]
Description=Synopsys License Server Daemon

[Service]
Type=simple
RemainAfterExit=yes
KillMode=process
ExecStart=/bin/sh -c "/path/to/eda/script/snpslmd.sh"

[Install]
WantedBy=multi-user.target

#
# Startup license server
#
% sudo systemctl daemon-reload
% sudo systemctl start snpslmd.service

#
# Enable license server onboot
#
% sudo systemctl enable snpslmd.service

#
# Check the status of the license server
#
% sudo systemctl status snpslmd.service
% ps aux | grep lmgrd | grep snpslmd
% lmstat

Unresolved issue:
Unable to stop license server by systemctl stop snpslmd.service

Starting from 2023, Siemens changes their EDA license managing utility.

Previous MGLS (Mentor Graphic License Server) doesn’t support EDA softwares of 2023 or later. Calibre 2023 may be still in the supporting list, but Tenssent 2023 isn’t for sure. Instead, SLS (Siemens License Server) is the successor of MGLS.

The SLS utility doesn’t need to be patched while EDA software itself should be patched and still be valid by OCAD 1patch v0.3.

The license file generated by MentorKG.exe is still available for SLS. All you need to do is to modify the DAEMON (2nd line) by replacing ‘mgcld’ with ‘saltd’.

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DAEMON saltd /PATH/TO/SLS/UTILITY/saltd

End user should set the environment variable SALT_LICENSE_SERVER, for example setenv SALT_LICENSE_SERVER 27001@licsrv. Some of old Mentor tools still check license within the old variable MGLS_LICENSE_FILE, so we need to set both variables with same value.

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setenv SALT_LICENSE_SERVER 27001@licsrv
setenv MGLS_LICENSE_FILE 27001@licsrv

Now enjoy the new Siemens/Mentor softwares of 2023 or later.

PS. how to check the availability of SLS floating license?

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% tessent -shell
% calibredrv