PrimeTime-PX Flow
PT-PX is PrimeTime with power analysis. It’s a tool within PT (requires separate license of PT-PX). PT-PX combines simulation time window to report power within a window.
Steps: Following are the steps to invoke PT-SI
0. invoke pt_shell normally
pt_shell-2012.12-SP3 -f scripts/run_power.tcl |tee logs/run_power.log => can be invoked in gui mode too.
run_power.tcl has following cmds:
1. set library, read gate level verilog netlist and spef file => same as in normal PT flow. pwr is calc for chosen PVT corner.
PrimeTime and Timing Derate
We learned OCV in a few other posts. However running OCV at 2 different PVT corners may not always be practical. For ex, consider the voltage drops seen on a chip due to IR. We may not be able to get lib at that particular voltage corner after accounting for the voltage drop due to IR. Similarly for temperature, we may not be able to lib for that exact temperature after accounting for on chip heating. Also, even if we are able to get these libs, ocv analysis requires running at 2 extreme corners. If we do not want to run analysis at 2 diff corners for ocv, we can run it at 1 corner only by specifying derating. Derating is an alternate approach where we speed up or slow down certain paths so that they can indirectly achieve same results as OCV. Derating is basically applying a certain multiplying factor to each gate delay so that the delay can be scaled up (by having a multiplying factor > 1), or can be scaled down (by having a multiplying factor < 1). The advantage of derate is that each and every gate in design can now be customized to have a particular delay on it. With OCV analysis, we weren’t able to do this, as the flow just chose b/w WC and BC lib and applied one or the other to each gate in design. Here, we first choose a nominal voltage, for which we have library available, and then apply derate to achieve effects of Voltage and Temperature variations.
What Is OCV/AOCV/POCV/SOCV/LVF?
芯片在实际生产中，同一片晶圆上的不同区域的芯片，因为各种外部条件和生产条件的变化（variation），比如：工艺（Process），电压（Voltage），温度（Temperature）等，可能会产生不同的误差从而导致同一块晶圆上某些区域上的芯片里的晶体管整体速度变快或变慢，因此有了corner的概念。而与此同时，在同一块芯片上的不同区域，也会因为上述因素而有进一步的差异（variation），因此产生了OCV（On Chip Variation）的概念。
Corner vs. OCV
Synopsys Computer Platforms Roadmap
| Foundation | ROs | Linux O/S Versions | Windows Platform |
|---|---|---|---|
| U | 2023.06 | CentOS: 7.3+ RHEL: 7.3+; 8+ SLES: 12-SP4+; 15+ | Windows 10 Windows Server 2016 Windows Server 2019 |
| U | 2023.03 | ||
| U | 2022.12 | ||
| T | 2022.09 | CentOS: 7.3+ RHEL: 7.3+; 8+ SLES: 12-SP4+; 15+ | Windows 10 Windows Server 2016 Windows Server 2019 |
| T | 2022.06 | ||
| T | 2022.03 | ||
| S | 2021.12 | CentOS: 7.3+; 8+ RHEL: 7.3+; 8+ SLES: 12-SP4+; 15+ | Windows 10 Windows Server 2016 |
| S | 2021.09 | ||
| S | 2021.06 | ||
| R | 2021.03 | RHEL 6.6+, 7.x, 8+ CentOS 6.6+, 7.1.1503+, 8+ SLES 12+, 15+ | Windows7, 10Windows Server 2016 |
| R | 2020.12 | ||
| R | 2020.09 | ||
| Q | 2020.06 | RHEL 6.6+, 7.x, 8+ CentOS 6.6+, 7.1.1503+, 8+ SLES 12+, 15+ | Windows7, 10Windows Server 2008 R2, 2016 |
| Q | 2020.03 | ||
| Q | 2019.12 | ||
| P | 2019.09 | RHEL 6.6+, 7.x CentOS 6.6+, 7.x SLES 11.4+ and 12.x | Windows 7, 10Windows Server 2008 R2, 2016 |
| P | 2019.06 | ||
| P | 2019.03 | ||
| O | 2018.12 | RHEL 6.6+, 7.x CentOS 6.6+, 7.x SLES 11.4 and 12.x | Windows 7, 10Windows Server 2008 R2, 2016 |
| O | 2018.09 | ||
| O | 2018.06 | ||
| N | 2018.03 | RHEL 6.6+, 7.x SLES 11.x and 12.x | Windows 7, 8, 10 |
| N | 2017.12 | ||
| N | 2017.09 | ||
| M | 2017.06 | RHEL 6.6+, 7.x SLES 11.x and 12.x | Windows 7, 8, 10 |
| M | 2017.03 | ||
| M | 2016.12 |
OCV Evolution
EDA (Electronic Design Automation) cell characterization tools have been used extensively to generate models for timing, power and noise at a rapidly growing number of process corners. Today, model variation has become a critical component of cell characterization. Variation can impact circuit timing due to process, voltage, and temperature changes and can lead to timing violations, resulting in a costly re-spin of the design. While global variation is captured by analyzing the design at different process corners, local variation cannot be handled effectively with just the traditional corner-based static timing analysis (STA). As designers try to squeeze every ounce of power-performance-area (PPA), packing millions of transistors into the chip, local variation effects have become more and more prominent. In today’s most advanced nodes at 7nm and below, there is a strong need for innovative methods to reduce pessimism and to provide a better design margining methodology to accurately account for the impact of variation.
