| Design Level | Strategies |
|---|---|
| Operating System Level | Portioning, Power down |
| Software Level | Regularity, locality, concurrency |
| Architecture Level | Pipelining, Redundancy, data encoding |
| Circuit/Logic Level | Logic style, transistor sizing, energy recovery |
| Technology Level | Threshold reduction, multiple threshold devices |
| Traditional Techniques | Dynamic power reduction | Leakage power reduction | Other power reduction techniques |
|---|---|---|---|
| Clock gating | Clock gating | Minimize usage of LVt | Multiple oxide devices |
| Power gating | Power efficient circuits | Power gating | Power efficient circuits |
| Variable frequency | Variable frequency | Back biasing | Minimize capacitance by custom design |
| Variable voltage supply | Variable voltage supply | Reduce oxide thickness | |
| Variable device threshold | Voltage Islands | Use FinFET |