PrimeTime-PX Flow

PT-PX is PrimeTime with power analysis. It’s a tool within PT (requires separate license of PT-PX). PT-PX combines simulation time window to report power within a window.

Steps: Following are the steps to invoke PT-SI

0. invoke pt_shell normally

pt_shell-2012.12-SP3 -f scripts/run_power.tcl |tee logs/run_power.log => can be invoked in gui mode too.
run_power.tcl has following cmds:

1. set library, read gate level verilog netlist and spef file => same as in normal PT flow. pwr is calc for chosen PVT corner.

set search_path "$search_path /db/pdkoa/1533e035/current/diglib/pml48h/synopsys/bin"
set target_library PML48H_W_85_3_CORE.db
set link_library {* PML48H_W_85_3_CORE.db}

read_verilog /db/ATAGO/.../FinalFiles/digtop_final_route.v => read final routed netlist
current_design digtop
link

read_parasitics /db/ATAGO/.../FinalFiles/digtop_final_route_max.spef => read max spef file

2. set power analysis so that PTPX license is invoked

set power_enable_analysis true
set power_analysis_mode averaged

3. Read VCD file from one of the simulation (it needs to be gate level VCD file with back annotation of parasitics)

read_vcd /sim/ATAGO/.../sim1_max.vcd.gz -strip_path digtop_tb/IDUT/spi_regs -time {100489 800552} => strips module of interest so that pwr is reported starting from that module as top level. time is in ns.
report_switching_activity > reports/power_swtching.rpt => to examine tr/sp (see below) and vcd file syntax

4. report power

#check_power -verbose => prior to analysis, verifies that analysis i/p are valid
#update_power => This is needed for RTL VCD or when no vcd provided to propagate activity to nets/registers not annotated from RTL VCD file.
#report_switching_activity => to examine propagated values of tr/sp
#create_power_waveforms -cycle_accurate => to show pwr waveform
report_power > ./reports/power_summary.rpt
report_power -hier > ./reports/power_hierarchy.rpt
#report_power -cell -flat -net -hier -verbose -nosplit > power_detail.rpt
exit

Reports: power summary report

Static Power

Cell Leakage power. It’s leakage in the cell from VDD to VSS when cell i/p is at 0 or 1 (subthreshold lkg from src to drn since gates never turn off completely). It includes gate lkg also (gate lkg is captured only for i/p pins for each transistor, as o/p pin will finally connect to i/p pin of some other transistor. gate lkg is just the current flowing into the gate when i/p of gate is 0 or 1). cell lkg pwr number comes from .lib file. Pwr(lkg)=VI(subthreshold_lkg)+V*I(gate_lkg).
It has a default lkg pwr number for each cell, as well as different lkg pwr numbers depending on diff i/p values. ex:
cell (AN210_3V) {
cell_leakage_power : 1.731915E+00; => default lkg pwr
leakage_power () { => we can have many of these conditions for each cell
value : 1.718650E+00; => lkg pwr = 1.7pW when A=1 and B=0. pwr unit defined as pw by “leakage_power_unit : “1pW”;” in .lib file
when : “A&!B”;
}

Dynamic Power

A. internal pwr: This includes short ckt pwr when cell o/p is switching, as well as pwr due to charging of internal nodes in the cell (due to src/drn cap on all o/p nodes and gate cap on internal nodes). cell int pwr number comes from .lib file. Pwr(int)=EintTr where Tr=number of toggles/time.
Just like timing() section, we have internal_power() section for o/p pin. It shows int pwr for each combination of i/p values (as pwr will change due to short ckt current, drn/src cap changing). ex:
cell (AN210_3V) {
pin (Y) { => pwr is always for o/p pin, since i/p pin pwr is calcualted separately as switching pwr.
internal_power () { => pwr unit is in pJ = power unit(pW) * time_unit(s) (it’s energy, not power).
related_pin : “A”; => this is when o/p changes due to i/p pin A changing
rise_power (outputpower_cap4_trans5) { … 34.39 .. } => pwr under diff cap load on o/p pin, and diff slew on i/p pin
fall_power (outputpower_cap4_trans5) { … 34.39 .. } => fall_power is when o/p pin falls due to pin A rising/falling
}
internal_power () {
related_pin : “B”; => this is when o/p changes due to i/p pin B changing
rise_power (outputpower_cap4_trans5) { … 34.39 .. } => rise_power is when o/p pin rises due to pin B rising/falling
fall_power (outputpower_cap4_trans5) { … 40 .. } => 40pJ energy per toggle. Since time is in ns, pwr=mw??
}
}
}

B. switching pwr: This is due to charging/discharging of all the o/p load in design. This includes wire cap and gate cap on i/p pins which switch whenever o/p pin of any gate switches. Pwr(sw)=0.5CV^2*Tr. Tr=number of toggles/time.

Total_pwr = Pwr(lkg) + Pwr(int) + Pwr(sw) = Pwr(lkg) + EintTr + 0.5CV^2Tr (Pwr(lkg) and Eint come from.lib).
To calc avg pwr, static probability (Sp) is calcualted for all the nodes to be at 1 or 0. This is then used to calc lkg pwr for each cell. Toggle rate is caluclated for each node to calc dynamic pwr.
To calc peak pwr, vcd file is required to analyze events. It’s useful for dynamic IR drop. If vcd file not provided, then tool doesn’t know the seq of events. Merely toggle rate doesn’t tell it whether all nodes toggle at same time or not.
When VCd file is not provided, default Tr/Sp is applied to starting points (PI, black box o/p). default Tr/Sp can be modified using (power_default_toggle_rate, power_default_static_probability)