When you use Emacs-verilog to generate code automatically, tabs are inserted instead of whitespace by default. For myself I prefer not to have tabs in my Verilog code at all, even for line indent or signal alignment. Then how to achieve this in Emacs auto code?
Simply add two lines in your verilog-mode.el as below. Yeah, it’s done and enjoy!
1 | (setq-default tab-width 8) |
Check out everything about Emacs-verilog at https://veripool.org/verilog-mode/.