VLSI

Spyglass Constraint Convert From SDC to SGDC

  1. Abbreviations

    SDC ：Synopsys Design Constraints
    SGDC : Spyglass Design Constraints
    CDC : Clock Domain Crossing

  1. In Spygalss project file e.g. work.proj add this option

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    set_option sdc2sgdc { yes }

  2. Create $top.sgdc with content of follow 2 lines.

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    current_design $top
    sdc_data -file $PATH_TO_SDC_FILE

  3. After first run $top.sgdc Spyglass will generate auto SGDC format constraint files which are located at like,

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    ./work/$top/cdc/clock_reset_integrity/spyglass_reports/clock-reset/autoclocks.sgdc
    ./work/$top/cdc/clock_reset_integrity/spyglass_reports/clock-reset/autoresets.sgdc
    ./work/$top/cdc/clock_reset_integrity/spyglass_reports/clock-reset/generated_clocks.sgdc
    ./work/$top/cdc/clock_reset_integrity/spyglass_reports/clock-reset/generated_resets.sgdc

  4. Then you can cat above four auto SGDC files and replace all content of $top.sgdc.

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    cat ./work/$top/cdc/clock_reset_integrity/spyglass_reports/clock-reset/*.sgdc > $PATH_TO_SDC_FILE

  5. Now the $top.sgdc looks like,

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    current_design "xxx"
    #DEFINITE CLOCKS:
    clock -name "xxx.clk" -domain0 -tag SG_AUTO_TAG_1

    ##ASYNCHRONOUS RESETS##
    #DEFINITE RESETS:
    reset -name "xxx.rstn" -value 0